For some chip-to-chip communication schemes, forwarded clock signaling is used, whereby a clock signal for sampling data is transmitted along with the data. By transmitting the clock signal along with the data, noise introduced by the communication channel, such as phase jitter, is often common to both the clock signal and the data, so that transitions in the received clock signal still lie within the eye of the received data.
For some communication channels, multiple bits of data are transmitted over a plurality of transmission lines during each clock cycle. A clock receiver on the receiving chip receives the clock signal, and the output of the clock receiver is distributed to various functional units on the receiving chip. Such functional units include the various data receivers on the receiving chip for receiving the multi-bit data. A clock distribution network, such as one or more clock trees, may be used to distribute the output of the clock receiver. This is illustrated in FIG. 4, where a clock signal and data are transmitted from transmitting chip 402 to receiving chip 404 by way of transmission lines 406 and 408. The clock signal is received by clock receiver 410, and distributed by clock tree 412 to data receiver 414.
It is desirable for the distributed clock signal to be in phase with the received clock signal, so that the received data at the various data receivers are sampled within the eye of the data. This may be accomplished during an initialization, or training period, in which delay lines and phase interpolators are utilized in the clock distribution path, and are adjusted so that the distributed clock signal matches the received clock signal. However, after initialization, there may very likely be variations in the temperature and supply voltage that affect the performance of the clock distribution network, as well as the delay line and the phase interpolators. As a result, it may happen that the distributed clock signal is no longer well matched in phase to the received clock signal, and this may result in data detection errors. This may be especially acute in high performance systems.
It is desirable and useful to adjust a clock signal distributed on an integrated circuit by way of a clock distribution network so that it stays in phase with a received clock signal, even if the characteristics of the clock distribution network change due to temperature, supply voltage, or other variables.